SOI technology consists in separating a fine layer of silicon (a few nanometers thick) from a silicon substrate by a relatively thick layer of insulator (with a thickness of a few tens of nanometers as a general rule).
Integrated circuits made with SOI technology have a certain number of advantages. Such circuits generally consume less electricity for equivalent performance. Such circuits also induce lower parasitic capacitances, thus improving switching speed. Furthermore, the latch-up or parasitic triggering phenomenon encountered by MOS transistors in bulk technology can be avoided. Such circuits therefore are particularly well suited to SoC or MEMS type applications. It is generally noted that SOI integrated circuits are less sensitive to the effects of ionizing radiation and are hence more reliable in applications where such radiation could cause operational problems, especially in space applications. SOI integrated circuits can include, especially, SRAM random-access memories or logic gates.
Reducing the static consumption of logic gates while at the same time increasing their switchover speed is the subject of much research. Certain integrated circuits that are being developed integrate both low-consumption logic gates and high-switchover-speed logic gates. To generate both these types of logic gates on a same integrated circuit, the threshold voltage level of some transistors of high-access-speed logic gates is reduced and the threshold voltage of other transistors of low consumption logic gates is increased. In bulk technology, the threshold level modulation of the same type of transistors is done by differentiating their channel doping level. However, in FDSOI (Fully Depleted Silicon-On-Insulator) technology, the doping of the channel is almost zero (1015 cm−3). Thus, the channel doping levels in the transistors cannot show big variations. This means that the threshold voltages cannot be differentiated by their channel doping levels. One solution proposed in certain studies for making transistors of the same type with distinct threshold voltages is to integrate different gate materials for these transistors. However, making such an integrated circuit is impractical because it is technically difficult and economically prohibitive.
In order to have distinct threshold voltages for different transistors using FDSOI technology, there are also known ways of using a biased ground plane placed between a thin layer of insulating oxide and the silicon substrate. By manipulating the doping of the ground planes and their biasing, it is possible to define a range of threshold voltages for the different transistors. One could thus have low-voltage-threshold, or LVT transistors, high-voltage-threshold, or HVT transistors, and medium, or standard-voltage-threshold, also known as SVT transistors.
For certain functions of the circuit, it is possible to combine transistors of a same type, for example LVT or HVT transistors, in the same region. However, certain functions of the circuit require the contiguous joining of different types of transistors with ground planes having different biases. The design of such functions of the circuit proves to be relatively difficult because additional design constraints have to be taken into account. FIGS. 1a to 1c provide an example of pairs of transistors of different types, respectively HVT, SVT, and LVT type transistors.
FIG. 1a shows an example of a pair of HVT-type transistors, namely an nMOS transistor 1nH and a pMOS transistor 1pH. The transistors 1nH and 1pH are made with SOI technology. The transistors 1nH and 1pH are made on a silicon substrate layer 101H. The transistors 1nH and 1pH comprise respective buried insulating layers, 103nH and 103pH, separated from the substrate layer 101H by means of respective ground planes 102nH and 102pH and wells 112nH and 112pH. The insulating layers 103nH and 103pH are surmounted by an active silicon layer. The active silicon layer of the transistor 1nH comprises a source, a channel 104nH, and a drain. The active silicon layer of the transistor 1pH comprises a source, a channel 104pH, and a drain. The ground planes 102nH and 102pH enable the electrostatic control of the transistor to be improved by limiting the penetration of the electric fields generated by the drain and the source beneath the channel 104nH or 104pH. The reduction of the lateral electrostatic coupling reduces short-channel effects and limits the drain-induced depletion effect or drain-induced barrier lowering (DIBL) effect. The channels 104nH and 104pH are covered respectively with gate oxide layers 105nH and 105pH. The gate oxides 105nH and 105pH are surmounted by respective gate stacks comprising metal layers 108nH and 108pH and polysilicon layers 111nh and 111ph. The stacks are demarcated laterally by spacers 110nH and 110pH. Insulation trenches 106H, 107H and 109H are placed around the transistors 1nH and 1pH.
To obtain HVT type transistors, the ground planes have a thickness known as an ultra thin thickness, typically ranging from 10 to 100 nm. The ground plane 102nH has P-type doping and is biased to ground, and the ground plane 102pH has an N-type doping and is biased to Vdd. The wells 112nH and 112pH have respective P-type and N-type dopings. The ground planes 102nH and 102pH are biased by means of wells 112nH and 112pH respectively.
FIG. 1b shows an example of a pair of SVT-type transistors, namely an nMOS transistor 1nS and a pMOS transistor 1pS. The transistors 1nS and 1pS have substantially the same structure as the transistors 1nH and 1pH: they are made on a silicon substrate layer 101S comprising respective buried insulating layers 103nS and 103pS separated from the substrate layer 101H by means of the respective ground planes 102nS and 102pS and wells 112nS and 112pS. The insulating layers 103nS and 103pS are surmounted by an active silicon layer. The active silicon layer of the transistor 1nS has a source, a channel 104nS and a drain. The active silicon layer of the transistor 1pS has a source, a channel 104pS and a drain. The channels 104nS and 104pS are covered respectively with gate oxide layers 105nS and 105pS. The gate oxide layers 105nS and 105pS are surmounted by respective gate stacks comprising metal layers 108nS and 108pS and polysilicon layers 111nS and 111pS. The stacks are demarcated laterally by spacers 110nS and 110pS. Insulating trenches 106S, 107S and 109S are placed around the transistors 1nS and 1pS.
To obtain SVT type transistors, the ground planes have an ultra-thin thickness. The ground plane 102nS has an N-type doping and is biased to ground and the ground plane 102pS has P-type doping and is biased to Vdd. The wells 112nS and 112pS have respective P-type and N-type dopings. The biasing of the ground planes 102nS and 102pS is done by means of the wells 112nS and 112pS respectively.
FIG. 1c shows an example of a pair of LVT-type transistors, namely an nMOS transistor 1nL and a pMOS transistor 1pL. The transistors 1nL and 1pL have substantially the same structure as the transistors 1nH and 1pH: they are made on a silicon substrate layer 101L comprising respective buried insulating layers 103nL and 103pL separated from the substrate layer 101H by means of respective ground planes 102nL and 102pL and wells 112nL and 112pL. The insulating layers 103nL and 103pL are surmounted by an active silicon layer. The active silicon layer of the transistor 1nL has a source, a channel 104nL and a drain. The active silicon layer of the transistor 1pL has a source, a channel 104pL and a drain. The channels 104nL and 104pL are covered respectively with gate oxide layers 105nL and 105pL. The gate oxides 105nL and 105pL are surmounted by respective gate stacks comprising metal layers 108nL and 108pL and polysilicon layers 111nL and 111pL. The stacks are demarcated laterally by spacers 110nL and 110pL. Insulating trenches 106L, 107L and 109L are placed around the transistors 1nL and 1pL.
To obtain LVT type transistors, the ground planes have an ultra-thin thickness. The ground plane 102nL has N-type doping and is biased to Vdd, and the ground plane 102pL has P-type doping and is biased to ground. The wells 112nL and 112pL have respective N-type and P-type dopings. The biasing of the ground planes 102nL and 102pL is done by means of the wells 112nL and 112pL respectively.
If pairs of HVT and SVT transistors can be attached together on the same row or on adjacent rows, a pair of LVT transistors, on the contrary, cannot be adjacent to a pair of HVT or SVT transistors. Indeed, it can be necessary to modify the biasing of the ground planes to ground or to Vdd. Owing to these biases and dopings of the ground planes, shorting between wells or forward-biased P-N junctions can be generated.